1. Field of the Invention
The present invention relates generally to electronic circuits, and more particularly, to power factor correction circuits for the efficient delivery of electrical power to circuit loads.
2. Description of the Related Art
An alternating current (AC) passing through an electrical load is not always in phase with the driving voltage. In the design of a power delivery circuit, one main objective is to channel as much driving power to the load as possible, with minimal power loss in the transmission process.
FIG. 1 shows a simplified schematic drawing of a power delivery circuit generally designated by the reference numeral 2. The delivery circuit 2 includes an AC power supply 4 driving a load 6 through a transmission circuit 8. In this specification, the lower case alphabets are used to designate parameters that vary with time. For simplicity in illustration, suppose the voltage v generated from the power supply 4 is sinusoidal. The driving voltage v passing through the transmission circuit 8 and the load 6 generates a current i which is also sinusoidal out of the power supply 4.
As mentioned before, the driving voltage v and the current i are not always in phase with each other. FIG. 2 shows the relationship of the voltage v and current i as a function of time. Depending on the nature of the load 6, in this example, the current i lags behind the voltage v. The phase shift is designated by a phase shift angle .theta. and is shown in FIG. 2. Because of the phase shift angle .theta., not all the power generated by the power supply 4 is delivered to the load 6. Rather, the real portion of the total power p, that is, the actual power P.sub.r delivered to the load 6 is expressed by following algebraic expression: EQU p.sub.r =v i cos .theta. (1)
while the imaginary portion of the power p, P.sub.i is represented by another algebraic expression: EQU p.sub.i =v i sin .theta. (2) PA1 where p, p.sub.r and p.sub.i are all expressed in Watts.
The imaginary power p.sub.i is not at all absorbed and utilized by the load 6. Instead, the imaginary power p.sub.i is required to flow through the reactance component X of the input impedance Z which is the impedance encountered by the power supply 4 as shown in FIG. 1. The imaginary power P.sub.i has to be withdrawn from the power supply 4 in the form of current which, when passes through conductive paths such as the transmission circuit 8 shown in FIG. 1 results in undesirable Ohmic loss.
Reference is now returned to FIG. 2. The trigonometrical cosine of the phase angle .theta. between the driving voltage v and the current i for the circuit 2 shown in FIG. 1 is defined as power factor .gamma. of the power delivery circuit 2. In the design of a power delivery circuit, it is a constant design goal to adjust the power factor .gamma. as close to unity as possible for efficient delivery of power.
Various power factor correction schemes have been proposed. Disclosed in Spangler et al., "Electronic Fluorescent Ballast using a Power Factor Correction Techniques for Loads Greater than 300 Watts," Proceedings of the Sixth Annual Applied Power Electronics Conference, Mar. 10-15, 1991, pages 393-399, are various filter circuits used in the past to perform the function of power factor correction. The results have been reported not to be satisfactory.
Also disclosed in Spangler et el., supra (FIG. 5 of Spangler et al., supra) is a valley-fill circuit used for power factor correction and is duplicated herein for reference. The valley-fill circuit of Spangler et al., supra, is shown in FIG. 3.
The valley-fill circuit is designated by the reference numeral 10 which includes a rectifying circuit 12 having input leads 14A and 14B tied to a power supply 4. The output leads 16A and 16B of the rectifying circuit 12 are connected to a charge storage circuit 17. The charge storage circuit 17 comprises a diode D1 sandwiched between a pair of capacitors C1 and C2. There is also another diode D2 having the anode terminal connected to the cathode terminal of the diode D1. The cathode of the diode D2 is tied to the output node 16A. In a similar manner, there is yet another diode D3 having the cathode terminal connected to the anode of the diode D1. The anode of the diode D3 is attached to the other output node 16B. A load 6 is also connected across the nodes 16A and 16B.
FIG. 4 is a timing diagram which shows the input current i and the output voltage v.sub.o in response to the driving voltage v of the circuit 10, combined in one graphical representation for the purpose of illustrating the timing relationship. To simply the analysis, the output load 6 is assumed to have a high impedance. The output voltage v.sub.o in response to the input voltage v is first explained and reference is made to FIG. 4 in conjunction with FIG. 3.
During normal operation, when the driving voltage v is at the positive half-cycle, the diodes DA and DB in the rectifying circuit 12 are turned on while the diodes DC and DD are reverse-biased and are thus non-conducting. The capacitors C1 and C2 are charged through the diode D1. Diodes D2 and D3 are reverse-biased and are thus turned off. As such, the voltage at the output nodes 16A and 16B charges up in phase with the driving voltage v and a current i flows into the circuit 10 as shown in FIGS. 3 and 4. Switching from the positive half-cycle to the negative half-cycle, the node 16A is drifting toward the negative polarity while the node 16B is rising from the negative to the positive level. However, when the difference in voltage between the nodes 16A and 16B is about a diode drop (approximately 0.7 Volt), the diodes D2 and D3 conduct and the diode D1 is turned off. The capacitors C2 and C1 discharge through the diodes D2 and D3, respectively. The discharge is an exponential decay with a time constant which depends on the RC (resistance-capacitance) time constant of the current discharge path. The voltage decay is graphically illustrated as waveform trace 18 shown in FIG. 4.
During the negative half-cycle, the diodes DC and DD in the rectifying circuit 12 are turned on, while the diodes DA and DB are shut off. Thereafter, the circuit 10 substantially operates in the same manner as described above and is not repeated in here. The result is as shown in FIG. 4.
As is well known in the art, a capacitor acts as an open circuit to a constant driving voltage. For a sluggish voltage decay 18 with a long time constant, as is the case in here because the output load 6 has a high impedance, the output voltage v.sub.o behaves as if it were at a constant level. Thus, no current is withdrawn from the voltage supply 4 and the input current i during the period of output voltage decay 18 is zero as shown in FIG. 4. As a consequence, the current waveform for the input current i is truncated at the phase angle near the voltage polarity transitions designated by the reference numeral 21. The current spikes identified by the reference numeral 20 come chiefly from charging of the capacitors C1 and C2 after the time of the voltage decay 18. As mentioned before, a sluggish voltage decay 18 with a long time constant renders the output voltage v.sub.o to behave as if it were at a constant voltage level. Accordingly, the capacitors C1 and C2 act as a virtual short circuit to any sudden changes of output voltage v.sub.o deviated from the aforementioned constant voltage level. Consequently, there are sudden withdrawals of current i from the power supply 4 manifesting themselves as current spikes 20.
As is also known in the art, the current waveform i shown in FIG. 4, irregular in shape as it appears, can be broken down into its constituent sinusoidal harmonics under the Fourier analysis. For each sinusoidal harmonic of the current i, power delivered p.sub.r and the power factor .gamma. can be computed by the equations as described above. FIG. 5 shows the Fourier harmonics of the waveform of the input current i displayed in the frequency domain. There are multiple orders of harmonics 22 after the fundamental harmonic 24. Aggregating the power delivered p.sub.r and the power factor .gamma. for all the harmonics constitute respectively the overall power delivered p.sub.r and the main power factor .gamma. of the power delivery circuit 2. However, the higher order harmonics 22 have low power factors .gamma. which significantly degrade the overall power factor of the circuit 2. It is found that the performance of the circuit 2 is marginally close to IEC (International Electronic Conference) specifications under limited conditions, but not under general conditions. The operating results of the circuit 2 is summarized in Table 5 of Spangler et al., supra, which results will further be discussed in this specification.
Wide ranges of household appliances and industrial machines are driven by AC power. Power delivery circuits with high power factors not only conserve energy in general but also increase reliability and extend the lives of the these electrical products. Accordingly, there has been a long-felt need to provide power delivery circuits meeting the aforementioned criteria.